Students Launch Rocket

Virtual Platforms Co-Emulation becoming reality!

Virtual Platforms and Hardware Emulation are finally coming closer!

Cadence recently announced (end of April 2010) a partnership with embedded software dealer Wind River Systems and extended Palladium XP to offer unified verification solutions for SoCs. Incisive software extensions and Wind River's Simics Virtual Platform have been combined to enable co-emulation with Virtual platforms seamlessly. Cadence has joined the bandwagon of application driven approach to system design
and development.

I see it as a solid step of convergence of various platforms. Synopsys already is leading the pack with their flurry of VP acquisition and strong hold in VCS design simulations. But Synopsys lacks Emulation bench strength with HAPS marketshare and lack of co-emulation solution. Other strong players in Emulation industry are EVE & Mentor, I'd expect to see future announcements around co-emulation.

What is ESL

ESL stands for Electronic System Level. RTL has dominated EDA industry for over 20 years. Higher level of modeling needs are becoming very important to meet fast time to market requirements for highly complex designs which are becoming increasingly complex to validate at system level.

Electronic System Level is the high level abstraction of Hardware models in C++/ SystemC and other languages for use in design and verification flows. RTL (Register transfer level) description has been used over 20+ years to successfully design and verify development. But as design complexity has grown, conventional tools are too slow to design/ validate and release products with supporting Software. Higher level abstraction reduces Time to Market for products.

 

Modeling languages: SystemC

High level synthesis/ Embedded SW tools

As model is developed for various IPs, model developers don't know the behavior till these models are tested in Virtual Platforms or sytem level models. This leaves lots of issues in models untested and can be time consuming to find and fix. ESL development areas currently lacks support for robust testbench methodologies.

Also there is need for more constructs for HW-SW communication & SystemC driven synthesis tools that could eliminate 20 year old RTL flows.