Opportunities in Virtual Platforms:
• Language development: SystemC is becoming language of choice for Virtual Platforms. Other popular language could be C++ or C#. Why SystemC:
• SystemC offers ready made library to hardware designers, thus bringing SW & HW closer. Chip designers have huge legacy of training in RTL languages & IP code, they need a transitional language instead of pure C++ sharp turn. Chip designers are getting trained from Verilog to System Verilog & SystemC offers more natural transition.
• SystemC offers better timing constructs making language more suitable for Architectural exploration as well.
• C-Synthesis: Ideal scenarios is to let architects develop SystemC or C++ based models that get synthesized into netlists directly. So I’d expect huge potential of growth & development in higher level abstraction of synthesis tools.
• Co-Simulation: Mixed RTL & SystemC or C++ simulation
• Co-Emulation: Mixed C++/SystemC with FPGA or Emulation tools
• Architectural exploration with Virtual platforms. Architecture exploration using Virtual Platforms.
• HW/ SW boundaries –
• Timing accurate (approximate or loosely timed models) for busses for architectural exploration.
Monday, September 20, 2010
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