Need of cycle accurate models with VP

Need for Cycle accurate models in VPs:

Majority of Firmware testing (such as BIOS) is sufficient with higher abstraction models but several portions require cycle accurate HW behavior (such as Memory training/ programming) for which SW developers conventionally waited for Si to arrive.

Performance tuning & validation: Architects have to often wait for RTL to be avail or wait for Si for performance tuning. Architects can integrate timing accurate models into their ESL models as RTL becomes available.