VGA validation

Who needs to do VGA testing!!! Believe me, I have seen VGA testing as most overlooked validation area. And even designers often assume that IP blocks are ready to use without understanding the system level integration issues, esp in memory mapping/ space. When creating VGA validation environment, I have faced following problem numerous times in different projects:
* VGA spaced is accessed by host through IO mapped address acceses. A host control unit often fails to validate VGA space (due to legacy - always works!). Often VGA accesses will fail to arrive at proper design block. So first thing to check will be are these accesses showing up at VGA design block.

Creating an Emulator environment with Veloce:
We obtained legacy DOS based VGA tests. In a Si system, often a graphics card is plugged into PCIe port. DOS based tests access VGA thru IO mapped cycles to target card. And render outputs to display. Target design is synthesized into Emualtor box (such as Mentor or Cadence or EVE). A host PC is connected to emulator thru PCIe port (through a transactor or ICE in circuit emulation HW speed bridge board). DOS tests run on emulator.
For VGA frame sizes its a good enough setup, but for high resolution tests, it could take you "really long time" to render frames over Emulated PCIe port. Often back-door-memory accesses can speed up this testing.