Welcome to my blog

I am a validation architect, with 15+ years of work experience in Semi-conductor industry. I have worked on various aspects of making Si chips, working in :
* Si design & validation: addressing various aspects of development cycle, from concept to real high volume manufacturing
* Platform architecture & validation: addressing new use models of new technologies these Si products offer.

Currently I am working to address various needs of a product validation with main focus on reducing time to market by finding all bugs! & finding them early! I have actively contributed my validation expertise to following areas:
* Pre-Si validation - RTL simulators
* Push post-Si validation content in pre-Si domain: Given limitations of RTL simulators what content can be pushed upstream to find bugs early. And what enabling technologies I can deploy to be able to run that content (examples: VP/ Emulation/ Rapid Proto-typing).
* Post-Si validation: how to capture all bugs in Si & be able to debug them. Work on debuggers, test content tools, etc. In addition to working on Post-Si validation tools, I have worked extensively to push the content in Pre-Si. I have also worked extensively on "Si to RTL" tools to debug & fix the bugs
* SW co-validation: How to reduce Time to market by enabling SW validation (drivers, bios, some apps stack) with RTL or with C++ models
* Architectural Exploration: Enable architects with tools to validate architecture much before RTL is available.


I am working on finding ways to reduce time to market by enabling SW co-validation, system level validation, moving post-Si validation content in pre-Si etc. I work with product development teams to deploy these technologies and reduce risk for our projects. While I get paid to enable technologies & take them in product development flows & addressing gaps which product teams might run into. I am often using new technologies to have better validation partitioning in my chip architecture - utilize Virtual Platforms, Emulation, Rapid-prototyping (FPGA), Co-Simulation, SW Co-validation etc, to address validation needs.

I'll post when I feel like publishing - I want to write papers to share my learning with rest of industry and challenge industry to address gaps left. We all benefit from mutual learning....