Why Virtual Platforms over Emulation or Rapid Prototyping

For a new project, I recommend creating a validation master plan for entire duration of project. VP may allow you to create a system level model very early in your planning cycle. And as as various pieces of platforms are developed, these can be plugged back into common VP platform to add accuracy. Use FPGAs/ Emulation opportunistically for verifying RTL with system level model. Various teams in architecture, SW development, Si design/ validation, Post-Si validation teams can utilize VP platform by replacing higher abstraction level models with more accruate models & co-simulate or co-emulate with VP platform.

I am not advocating using VP to replace everything else in validation flow. But VP offers unique capabilities which other technologies might not. So apply VP to fill validation gaps. VP allows creating a hybrid validation system which can be scalable for accuracy, speed, cost-effectiveness throughout the project.

* For Architectural exploration VP is a good technology to deploy. For new architecture definition, often RTL won't be ready for a long time. Doing Emulation or FPGA prototyping with unhealthy RTL is not efficient. VP can add clear value by providing a system level models; where architects can easily plug their models into and test them out.

* Early SW development: RTL simulators are simply too slow. Emulation & FPGA prtotyping systems are too expensive to offer reasonable models for SW teams to use. VP can offer cost effective solution