Verilog simulators and tools

Here are some compiled links for tools available for ASIC designers.


Simulators

• Aldec : This simulator from Aldec supports VHDL, Verilog, SystemC, SystemVerilog, PSL. You name it and it supports it. I could not verify the SV testbench support, other than that everything else looks same as Modelsim. You can even use it to replace your existing Modelsim/VCS/NCverilog licenses.
• Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. A $100 version is available, but I wonder what good this can do to Students ?
• Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.
• MPSim : Axiom's MPSim is an integrated verification environment combining the fastest simulator in the industry with advanced testbench automation, assertion-based verification, debugging, and coverage analysis. Personally I have seen this simulator to be faster then NCsim, it comes with build in Vera and SV support.
• NCVerilog : This is the compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations.
• Silos : I don't know if anyone is using this, Use to be fast and stable.
• Smash : mixed signal (spice), Verilog, VHDL simulator.
• VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools.
• VeriLogger Extreme : High-performance compiled-code Verilog 2001 simulator. This simulator has a very easy to use debugging environment that includes a built-in graphical test bench generator. The top-level module ports can be extracted into a timing diagram window that lets the user quickly draw waveforms to describe input stimulus. The test bench is generated automatically and results are displayed in the timing diagram window.
• Verilog-XL : This is the most standard simulator in the market, as this is the sign off simulator.
• Veritak : Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features. It is integral environment including VHDL to Verilog translator, syntax highlight editor (Veripad), class hierarchy viewer ,multiple waveform viewer ,source analyzer,and more --available for Windows XP/2000. If you are looking for fast verilog HDL simulator with very good GUI for professional use, while keeping extremely inexpensive price , this is it. You can try Veritak for free for two weeks. This simulator costs around $50.

   

   

Free Simulators

• Cver : Cver is an interpreted Verilog simulator. It follows the 1995 IEEE P1364 standard LRM with some features from Verilog 2000 P1364 standard. Although, because it is used in large company design flows, various changes from the P1364 standard have been made to match results of other simulators. It implements full PLI including PLI vpi_ application programing interface (API) as defined by Verilog 2000 LRM.
• Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well. All my tutorials are compiled on this compiler.
• Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.
• Verilogger : The evaluation version is a free 1000 line free Verilog simulator plus an automatic test bench generation tool. Student versions start at $70 for 6 months.
• Veriwell : This is a very good simulator. Supports PLI and verilog 1995.

       

VCD Viewer

• Dinotrace : Freeware VCD viewer from veritools
• GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
• nWave : One of the best VCD viewer, with support for large VCD dumps.
• Undertow : Undertow waveform viewer.
• WaveViewer : SynaptiCAD's freeware VCD viewer also supports analog signal display and SPICE import. A proprietary compressed waveform format allows it to compress VCD files by 200x, making it a very fast viewer.
• Waview : Free multi platform VCD waveform viewer.

   

Code Coverage

• Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process. These tools include HDL checking, coverage analysis, test suite analysis and FSM analysis. The environment includes an extensible flow manager for easy incorporation of custom verification flows. Verification Navigator supports Verilog, VHDL and mixed language designs and integrates seamlessly with all leading simulation environments.
• SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design. Verisity's SureCov measures FSM and code coverage with the lowest simulation overhead of any tool available, and without requiring changes to the source design. The SureSight graphical user interface shows exactly which parts of the design have been covered and which have not.
• Code Coverage Tool : A freeware code coverage tool. Code coverage tool is a Verilog code coverage analysis tool that can be useful for determining how well a test suite is covering the design under test.

   

   

Linting

• HDLint : A power full linting tool for VHDL and Verilog.
• Leda : Leda is a code purification tool for designers using the Verilog® and VHDL Hardware Description Language (HDL). Leda is uniquely qualified to analyze HDL code pre-synthesis and pre-simulation and is totally compatible with all popular synthesis and simulation tools and flows. By automating more than 500 design checks for language syntax, semantics and questionable synthesis/simulation constructs, Leda detects common as well as subtle and hard-to-find code defects, thus freeing designers to focus on the art of design.
• nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system.
• SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks the most complete lint tool on the market.

    Utils

• FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs.
• Jove : The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language. Jove has been tested extensively with Synopsys VCS and to a lesser extent with the GPL version of cver by Pragmatic C Software.
• Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.
• Teal : open source c++ class library for verification
• TestBencher Pro : Generates bus-functional models and test benches from language independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. Generates code for Verilog, VHDL, and SystemC.
• TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams. The waveforms can easily be exported to other Window programs, such as Microsoft Word, for use in writing design specifications. TimeGen is less price compared to other tools.
• Timing Diagrammer Pro : A professional timing diagram editor with an unbeatable feature set. Performs true full-range min/max timing analysis to help you find and eliminate all timing violations and race conditions. Also automatically calculates critical paths and adjusts for reconvergent fanout. Inserting diagrams into word processors is painless, thanks to a variety of image capture formats.
• Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation.
• WaveFormer Pro : Generates VHDL, Verilog, and SPICE code, and Patter Generator stimulus from timing diagrams. Import waveforms from HDL simulators, HP logic analyzers, VCD files, or draw them using the built-in timing diagram editor. Automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing, perform RTL level simulation, and generate synthesizable models directly from Boolean and registered logic equations.

SystemC Tools:
FSM to SystemC generator: http://hvg.ece.concordia.ca/Publications/TECH_REP/FSMSC_TR07.html
TLM to RTL transactor generator:

C++ Development Tools

* Visual Studio 2008: Integrated Development Environment
* Incredibuild is a system that distributes the compilation across many machines. Compile your model on several machines to reduce build times while utilizing PCs available.
* Memory Leak detect
* Code optimization
* MP

ESL Market Dynamics & Trends

Opportunities in Virtual Platforms:
• Language development: SystemC is becoming language of choice for Virtual Platforms. Other popular language could be C++ or C#. Why SystemC:
• SystemC offers ready made library to hardware designers, thus bringing SW & HW closer. Chip designers have huge legacy of training in RTL languages & IP code, they need a transitional language instead of pure C++ sharp turn. Chip designers are getting trained from Verilog to System Verilog & SystemC offers more natural transition.
• SystemC offers better timing constructs making language more suitable for Architectural exploration as well.
• C-Synthesis: Ideal scenarios is to let architects develop SystemC or C++ based models that get synthesized into netlists directly. So I’d expect huge potential of growth & development in higher level abstraction of synthesis tools.
• Co-Simulation: Mixed RTL & SystemC or C++ simulation
• Co-Emulation: Mixed C++/SystemC with FPGA or Emulation tools
• Architectural exploration with Virtual platforms. Architecture exploration using Virtual Platforms.
• HW/ SW boundaries –
• Timing accurate (approximate or loosely timed models) for busses for architectural exploration.

Regression Framework & Testing Framework

For a validation person, its imperative to have a regression framework of choice. I work in Virtual Platforms where I use .NET framework with Visual studio for my work. Several of my models come from other environments as well. In this article, I am going to describe infrastructure for build and testing models, with an example of virtual platform project.

For a given project I would describe frameworks as example, though several other possible frameworks are available. For maintaining your source code, you need a Source code repository - such as SVN. You need to setup a test Test Framework - Py.test (python.org) or Junit. And you need to build your models on a desired frequency such as daily, weekly, or other duration. You can use a continous build Framework - Cruisecontrol (ccnet.org)


Test Framework: Py.test
Unit level testing is very important for software projects. For complex large projects, development teams need to maintain a nightly regression infrastructure to avoid any 'bad code' making into tree of your code base and destroying the project.

py lib has several namespaces that help automate testing, such as: py.test - write/ deploy unit and functional tests across multiple machines; and others py.code, py.path. py.xml, py lib scripts, py.io, py.log etc.


py.test is a command line tool to collect, run and report about automated tests. It can be used to run a single test to several 10's of K tests. By default, all python modules with a test_*.py filename are inspected for finding tests:

    * functions with a name beginning with test_
    * classes with a leading Test name and test prefixed methods.
    * unittest.TestCase subclasses


Regression framework

I can use Cruisecontrol to setup nightly or weekly builds for a software project. Cruisecontrol will provide automated web reports/ email notifications. CruiseControl is a framework for a continuous build process. It includes, but is not limited to, plugins for email notification, Ant, and various source control tools. A web interface is provided to view the details of the current and previous builds. It allows one to perform a continuous integration of any software development process.CruiseControl is free, open-source software, distributed under a BSD-style license. It was originally created by employees of ThoughtWorks to allow for continuous integration on a project they were working on. It was later extracted into a stand-alone application.There is a version of CruiseControl for .NET called CruiseControl.NET (aka CCNet) and a version for Ruby called CruiseControl.rb.

VCS Simulator features from Synopsys

I am covering only new features that interested me to investigate further.

Simulation speed-up by 2X utilizing Multi-core technology: 
VCS multi-core technology allows users to cut down verification time for long-running tests. VCS offers two robust use models: design-level parallelism (DLP) and application-level parallelism (ALP). DLP enables users to concurrently simulate multiple instances of a core, several partitions of a large design, or a combination of the two. Application-level parallelism (ALP) allows users to run testbenches, assertions, coverage and debugging concurrently on multiple cores. The combination of DLP and ALP optimizes VCS performance over multicore CPUs.

Auto-partitioning:

Comprehensive Coverage Tool -- Echo:
Comprehensive coverage includes code coverage, functional coverage and assertion coverage. Unified coverage aggregates all aspects of coverage in a common database, thereby allowing queries and useful unified report generation. The unified coverage database offers 2x to 5x improvement in merge times and up to 2x reduction in disk space usage, which is useful for large regression environments
For large designs coverage information is becoming extremely important to know when to sign-off your chip for tape-out.


Magnitude faster constraint solver:

VCS multicore technology also supports design-level auto-partioning, file system database (FSDB) parallel dumping, and switching activity interchange format (SAIF) parallel dumping.

Students Launch Rocket

Virtual Platforms Co-Emulation becoming reality!

Virtual Platforms and Hardware Emulation are finally coming closer!

Cadence recently announced (end of April 2010) a partnership with embedded software dealer Wind River Systems and extended Palladium XP to offer unified verification solutions for SoCs. Incisive software extensions and Wind River's Simics Virtual Platform have been combined to enable co-emulation with Virtual platforms seamlessly. Cadence has joined the bandwagon of application driven approach to system design
and development.

I see it as a solid step of convergence of various platforms. Synopsys already is leading the pack with their flurry of VP acquisition and strong hold in VCS design simulations. But Synopsys lacks Emulation bench strength with HAPS marketshare and lack of co-emulation solution. Other strong players in Emulation industry are EVE & Mentor, I'd expect to see future announcements around co-emulation.

What is ESL

ESL stands for Electronic System Level. RTL has dominated EDA industry for over 20 years. Higher level of modeling needs are becoming very important to meet fast time to market requirements for highly complex designs which are becoming increasingly complex to validate at system level.

Electronic System Level is the high level abstraction of Hardware models in C++/ SystemC and other languages for use in design and verification flows. RTL (Register transfer level) description has been used over 20+ years to successfully design and verify development. But as design complexity has grown, conventional tools are too slow to design/ validate and release products with supporting Software. Higher level abstraction reduces Time to Market for products.

 

Modeling languages: SystemC

High level synthesis/ Embedded SW tools

As model is developed for various IPs, model developers don't know the behavior till these models are tested in Virtual Platforms or sytem level models. This leaves lots of issues in models untested and can be time consuming to find and fix. ESL development areas currently lacks support for robust testbench methodologies.

Also there is need for more constructs for HW-SW communication & SystemC driven synthesis tools that could eliminate 20 year old RTL flows.

Carbon Design Systems

For SoC designs typically IP blocks are received (like 80% design reuse) in RTL formats. Conventionally companies hire contractors to recode blocks in SystemC. For new coding RTL models are available late & converting them to SystemC could be time consuming. Companies hire consultant services to model & create SystemC models. Carbod design studio lets make SystemC models very quickly from existing IPs (in RTL)

Carbon Model Studio can save time while ensuring accuracy in modeling. SystemC coders refer to Specs & sometimes reverse engineer to model accurately. CMS allows converting RTL for OSCI-SystemC simulation. Carbon design systems offers tools to create cycle accurate models quickly from RTL (VHDL/ Verilog). RTL models are compiled into C like linkable objects that can be simulated with other OSCI SystemC Simulators.

 Following diagram shows a simple flow of converting RTL for Virtual Platforms.

I did not get a chance to investigate limitations of Carbon model studios, if any of readers would like to share some experiences, please post.
To do list:

* How to validate SystemC models against RTL? Can RTL designers use VP for reference in validation?
* Comparison to FPGA prototyping
* Investigate robustness of CMS,

About Carbon Design Systems:
Founded in:
Products:
Number of Employees:
Equity/ Financing:

Need of cycle accurate models with VP

Need for Cycle accurate models in VPs:

Majority of Firmware testing (such as BIOS) is sufficient with higher abstraction models but several portions require cycle accurate HW behavior (such as Memory training/ programming) for which SW developers conventionally waited for Si to arrive.

Performance tuning & validation: Architects have to often wait for RTL to be avail or wait for Si for performance tuning. Architects can integrate timing accurate models into their ESL models as RTL becomes available.

BIOS POST Code Testing

BIOS POST codes are still relevant and a Virtual Platform Engineer might spend some time as engineers bring up the platform for first time. So its important to know the basics. Recently BIOS is being replaced with EFI.

When Computer boots, pre-boot code executed is called Power-On-Self_test. When a machine is powered on, its tested for basic functions with a special BIOS code called POST.  For a PC, BIOS reports messages on IO port 80. Using post-code, it can be identified what's going on in the machine.

Using a BIOS diagnostics card (e.g. PCI based card etc), Post codes can be displayed on a 2 segment LED display. Codes can be deciphered from BIOS manuals to understand what's going on in the sequence.

Here are some manuals that can be found on Phoenix/ AMI websites:

Phoenix technologies: Medallion BIOS™ Version 1.00

AMI: AMIBIOS8

APTIO: AMI

As an example, while working with my virtual machine, I reached boot sequence post code F4, which meant that it's a checkpoint, where Firmware has been loaded. Some platform teams put special codes for F5-F8 for attaching various tools to virtual platforms.

Applications of Virtual Platforms

How are people using power of Virtual Platforms:

• Power On readiness
• Post-Si validation readiness
• Driver development
• Embedded OS, OS/ BIOS Development

Virtual Platforms offers capabilities to Analyze, debug (visibility), controllability  over a Simulator SW Developers used in the past. Such capability is available to SW developers much before Si is available.

Virtual Platforms are not closed simulation models, but allow access to underlying physical HW such as configuring, allow visibility for debug etc. VP allows interfaces to “real world” e.g. a VP can access Internet via an Ethernet connection between VP & network in physical world; VP can talk to PCMCIA cards in PCMCIA slots of PC.Remote debugging is also possible on virtual platforms

Blogs

http://docs.google.com/View?id=ddgn5m5q_64gwg8q7fp

Hierarchical Approach to Platform Design

 

Key Terms: Hierarchical design; Platform Based Design; Block Based Designs for SoCs; Mapping Platform design to components (virtual or real).

 

One of most crucial decisions of design planning is what methodology you'd chose? A system designer creates platform level models in C++/ SystemC called Virtual Platforms. These platforms require some hierarchical approach to address following concerns:

a) Long term, it'll be desired to synthesize platform models into RTL description. Hierarchitecal design makes it possible to bridge gap between definition of a very high level model & actual implementation.

b) Platform design methodologies allow modifying SW code as its too hard to modify HW pieces in high level platform models. Hierarchical models allow to make modifications in HW along with SW.

c) its very hard to model performance in high level system models. Hier approach allows introducing performance processes as needed.

Debug on Virtual Platfoms:

Debug is a very important aspect of acceptance of VP in teams where a VP developers depends on collaboration with HW/ SW development teams.
This article discusses some of the debug hooks a VP engineer builds into the platform:

SW debug tools-

* UART: UART is a very primitive RS-232 based debug port, as system boots for first time, BIOS developers often use UART to print all debug messages on the port. PCI Config policy, Processor policy etc can be dumped, SPD from DIMMs, MRC=Memory Reference Code  on UART during run time.

* BIOS Diagnostics Post Code: A 2 segment display indicating BIOS POST codes

* Checkpoint: Code developers insert checkpoint codes to indicate flow of execution.

* Registers dumps
* Memory Dumps

Virtual Platforms

With SoC & complex systems, Virtual Platforms are gaining grounds. Processor industry is going through big change where Wintel domination was shattered with SoC/ Multi-core / Multi-processor based platforms.

As Si companies focus on providing "proven-IPs" it becomes system challenge to revenue generation. Time to Market is gated by System development.


Virtual Platforms allow SW developers to start testing their software stacks much before Si is available. VP doesn't replace need of Si, but allows early development & thus reducing TTM

VGA validation

Who needs to do VGA testing!!! Believe me, I have seen VGA testing as most overlooked validation area. And even designers often assume that IP blocks are ready to use without understanding the system level integration issues, esp in memory mapping/ space. When creating VGA validation environment, I have faced following problem numerous times in different projects:
* VGA spaced is accessed by host through IO mapped address acceses. A host control unit often fails to validate VGA space (due to legacy - always works!). Often VGA accesses will fail to arrive at proper design block. So first thing to check will be are these accesses showing up at VGA design block.

Creating an Emulator environment with Veloce:
We obtained legacy DOS based VGA tests. In a Si system, often a graphics card is plugged into PCIe port. DOS based tests access VGA thru IO mapped cycles to target card. And render outputs to display. Target design is synthesized into Emualtor box (such as Mentor or Cadence or EVE). A host PC is connected to emulator thru PCIe port (through a transactor or ICE in circuit emulation HW speed bridge board). DOS tests run on emulator.
For VGA frame sizes its a good enough setup, but for high resolution tests, it could take you "really long time" to render frames over Emulated PCIe port. Often back-door-memory accesses can speed up this testing.

Validation Strategy

You can't have a "generic" validation strategy for a project. But here is how I look at validation:

* Projects with several new features
VP/ Feature specific RP/ Emulation

* Projects with incremental new features
Emulation


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Evaluation Criteria

For Validation tools, such as Emulation or FPGA prototyping, here is simple litmus test of a soln:
* Capacity - whats cost of building model for current gen & next gen to reduce equip cost
* Performance - what performance I get with RTL models, with co-sim such as SCEMI/DPI/PLI
* Debug - what's visibility, ease of developing debuggers for RTL designers & debuggers for SW teams
* Time to use - First models efforts, model-to-model efforts, stability etc

Why Virtual Platforms over Emulation or Rapid Prototyping

For a new project, I recommend creating a validation master plan for entire duration of project. VP may allow you to create a system level model very early in your planning cycle. And as as various pieces of platforms are developed, these can be plugged back into common VP platform to add accuracy. Use FPGAs/ Emulation opportunistically for verifying RTL with system level model. Various teams in architecture, SW development, Si design/ validation, Post-Si validation teams can utilize VP platform by replacing higher abstraction level models with more accruate models & co-simulate or co-emulate with VP platform.

I am not advocating using VP to replace everything else in validation flow. But VP offers unique capabilities which other technologies might not. So apply VP to fill validation gaps. VP allows creating a hybrid validation system which can be scalable for accuracy, speed, cost-effectiveness throughout the project.

* For Architectural exploration VP is a good technology to deploy. For new architecture definition, often RTL won't be ready for a long time. Doing Emulation or FPGA prototyping with unhealthy RTL is not efficient. VP can add clear value by providing a system level models; where architects can easily plug their models into and test them out.

* Early SW development: RTL simulators are simply too slow. Emulation & FPGA prtotyping systems are too expensive to offer reasonable models for SW teams to use. VP can offer cost effective solution

Welcome to my blog

I am a validation architect, with 15+ years of work experience in Semi-conductor industry. I have worked on various aspects of making Si chips, working in :
* Si design & validation: addressing various aspects of development cycle, from concept to real high volume manufacturing
* Platform architecture & validation: addressing new use models of new technologies these Si products offer.

Currently I am working to address various needs of a product validation with main focus on reducing time to market by finding all bugs! & finding them early! I have actively contributed my validation expertise to following areas:
* Pre-Si validation - RTL simulators
* Push post-Si validation content in pre-Si domain: Given limitations of RTL simulators what content can be pushed upstream to find bugs early. And what enabling technologies I can deploy to be able to run that content (examples: VP/ Emulation/ Rapid Proto-typing).
* Post-Si validation: how to capture all bugs in Si & be able to debug them. Work on debuggers, test content tools, etc. In addition to working on Post-Si validation tools, I have worked extensively to push the content in Pre-Si. I have also worked extensively on "Si to RTL" tools to debug & fix the bugs
* SW co-validation: How to reduce Time to market by enabling SW validation (drivers, bios, some apps stack) with RTL or with C++ models
* Architectural Exploration: Enable architects with tools to validate architecture much before RTL is available.


I am working on finding ways to reduce time to market by enabling SW co-validation, system level validation, moving post-Si validation content in pre-Si etc. I work with product development teams to deploy these technologies and reduce risk for our projects. While I get paid to enable technologies & take them in product development flows & addressing gaps which product teams might run into. I am often using new technologies to have better validation partitioning in my chip architecture - utilize Virtual Platforms, Emulation, Rapid-prototyping (FPGA), Co-Simulation, SW Co-validation etc, to address validation needs.

I'll post when I feel like publishing - I want to write papers to share my learning with rest of industry and challenge industry to address gaps left. We all benefit from mutual learning....